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lxt915 simple quad ethernet repeater datasheet the lxt915 is an integrated multi-port repeater designed for mixed-media networks. it provides all the active circuitry required for the repeater function in a single cmos device. it includes one attachment unit interface (aui) port and four 10base-t transceivers. the aui port allows connection of an external transceiver (10base-2, 10base-5, 10base-t or foirl) or a drop cable. the 10base-t transceivers are entirely self-contained with internal filters that simplify the design work required for fcc-compliant emi performance. an inter-repeater backplane (irb) interface allows 128 or more 10base-t ports to be cascaded, creating a large single-segment multi-port repeater. the lxt915 requires only a single 5-volt power supply due to its advanced cmos fabrication process. applications product features remote or stand-alone unmanaged hubs stackable unmanaged hubs four integrated 10base-t transceivers and one aui transceiver on a single chip six integrated led drivers with four unique operational modes on-chip transmit and receive filtering automatic polarity detection and correction synchronous or asynchronous inter- repeater backplane supports ?hot swapping? inter-repeater backplane allows cascaded repeaters, linking 128 or more 10base-t ports packaged in 64-pin pqfp as of january 15, 2001, this document replaces the level one document order number: 249343-002 lxt915 ? simple quad ethernet repeater . february 2001 ( datasheet : )
datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the lxt915 may contain design defects or errors known as errata which may cause the product to deviate from published specifica tions. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel?s website at http://www.intel.com. copyright ? intel corporation, 2001 *third-party brands and names are the property of their respective owners.
datasheet 3 simple quad ethernet repeater ? lxt915 contents 1.0 lxt915 pin assignments and signal descriptions ...................................................... 8 2.0 lxt915 functional description .....................................................................................12 2.1 introduction..........................................................................................................12 2.2 external interfaces ..............................................................................................12 2.2.1 10base-t ports .....................................................................................12 2.2.2 aui port..................................................................................................12 2.2.3 inter-repeater backplane ......................................................................12 2.2.3.1 synchronous irb operation......................................................13 2.2.3.2 asynchronous irb operation ....................................................13 2.3 internal repeater circuitry ..................................................................................13 2.4 initialization..........................................................................................................14 2.5 10base-t port operation ...................................................................................16 2.5.1 10base-t reception .............................................................................16 2.5.2 polarity detection and correction...........................................................16 2.5.3 10base-t link integrity testing ............................................................16 2.5.4 10base-t transmission ........................................................................16 2.6 aui port operation ..............................................................................................17 2.6.1 aui reception ........................................................................................17 2.6.2 aui transmission ...................................................................................17 2.7 collision handling................................................................................................17 2.8 led display.........................................................................................................17 2.8.1 led mode 0 (default).............................................................................17 2.8.2 led mode 1 ...........................................................................................18 2.8.3 led mode 2 ...........................................................................................18 2.8.4 led mode 3 ...........................................................................................18 3.0 lxt915 application information ...................................................................................21 3.1 layout requirements ..........................................................................................21 3.1.1 the twisted pair interface .....................................................................21 3.1.2 the rbias pin .......................................................................................21 3.2 unmanaged hub application...............................................................................21 3.3 magnetics requirements.....................................................................................25 3.3.1 the twisted pair interface .....................................................................25 3.3.2 component selection .............................................................................25 4.0 lxt915 test specifications ...........................................................................................26 5.0 lxt915 mechanical specifications ...............................................................................30
lxt915 ? simple quad ethernet repeater 4 datasheet figures 1 lxt915 block diagram ......................................................................................... 7 2 lxt915 pin assignments...................................................................................... 8 3 global state machine.......................................................................................... 14 4 partitioning state diagram .................................................................................. 15 5 integrated led driver indications ....................................................................... 20 6 lxt915 8-port unmanaged hub application, led mode 1 selected (1 of 2)..... 23 7 lxt915 8-port unmanaged hub application led mode 1 selected (2 of 2)...... 24 8 inter-repeater bus timing .................................................................................. 29 9 lxt915 package specifications ......................................................................... 30 tables 1 twisted-pair port signal descriptions ................................................................... 9 2 aui port signal descriptions................................................................................. 9 3 control, status and miscellaneous signal descriptions........................................ 9 4 inter-repeater backplane signal descriptions ................................................... 10 5 lxt915 power supply signal descriptions......................................................... 11 6 led mode selection ........................................................................................... 18 7 mode 0 led truth table (default) ...................................................................... 18 8 mode 1 led truth table..................................................................................... 18 9 mode 2 led truth table..................................................................................... 19 10 mode 3 led truth table..................................................................................... 19 11 manufacturers magnetics list ............................................................................ 25 12 absolute maximum ratings ................................................................................ 26 13 recommended operating conditions ................................................................. 26 14 i/o electrical characteristics1 ............................................................................. 26 15 aui electrical characteristics.............................................................................. 27 16 tp electrical characteristics ............................................................................... 27 17 irb electrical characteristics.............................................................................. 27 18 switching characteristics .................................................................................... 28 19 inter-repeater bus timing .................................................................................. 29
datasheet 5 simple quad ethernet repeater ? lxt915 revision history date revision page description february 2001 002 26 i/o electrical characteristics table: supply current under max: change value from 180 to 240. under test conditions: add text: ? 100 ? test load, no leds ? . add table note to value: supply current may vary depending on the transformer, led, and resistor selections. swapped values for v ih and v ihreset.

simple quad ethernet repeater ? lxt915 datasheet 7 figure 1. lxt915 block diagram control twisted-pair port #1 tp port #2 f tp port #3 f tp port #4 f aui port (dte only) repeater (state machine, timing recovery, fifo, ect.) inter-repeater backplane port led drivers filter 4 4 4 ledm0 ledm1 do/di do/di do/di dop don dip din dop don dip din cip cin sysclk irena irden ircfs ircol irdat bclkio 4 ledtp1-4 ledaui ledcf a/sync dsqe reset
lxt915 ? simple quad ethernet repeater 8 datasheet 1.0 lxt915 pin assignments and signal descriptions figure 2. lxt915 pin assignments package topside markings marking definition part # lxt915 is the unique identifier for this product family. rev # identifies the particular silicon ? stepping ? (refer to specification update for additional stepping information.) lot # identifies the batch. fpo # identifies the finish process order. 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 vcc vcc irena irdat irden ircfs ircol gnd bclkio sysclk a/sync gnd ledm0 gnd reset dsqe vcc vcc ledcf ledtp1 ledtp2 ledtp3 ledtp4 ledaui gnd ledm1 gnd rbias gnd auidop auidon auidip auidin auicip auicin gnd tpdon4 tpdop4 vcc tpdop3 tpdon3 gnd tpdon2 tpdop2 vcc tpdop1 tpdon1 gnd tpdin4 tpdip4 vcc tpdip1 tpdin1 tpdip2 tpdin2 tpdip3 tpdin3 vcc LXT915QC n/c n/c n/c n/c n/c n/c 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 vcc vcc irena irdat irden ircfs ircol gnd bclkio sysclk a/sync gnd ledm0 gnd reset dsqe vcc vcc ledcf ledtp1 ledtp2 ledtp3 ledtp4 ledaui gnd ledm1 gnd rbias gnd auidop auidon auidip auidin auicip auicin gnd tpdon4 tpdop4 vcc tpdop3 tpdon3 gnd tpdon2 tpdop2 vcc tpdop1 tpdon1 gnd tpdin4 tpdip4 vcc tpdip1 tpdin1 tpdip2 tpdin2 tpdip3 tpdin3 vcc n/c n/c n/c n/c n/c n/c LXT915QC xx xxxxxx xxxxxxxx part # lot # fpo # rev #
simple quad ethernet repeater ? lxt915 datasheet 9 table 1. twisted-pair port signal descriptions pin symbol i/o description 44 45 42 41 38 39 36 35 tpdop1 tpdon1 tpdop2 tpdon2 tpdop3 tpdon3 tpdop4 tpdon4 o o o o o o o o twisted-pair data outputs (positive and negative). these pins are the positive (tpdop1-4) and negative (tpdon1-4) outputs to the network from the respective twisted- pair ports. 54 53 52 51 50 49 48 47 tpdip1 tpdin1 tpdip2 tpdin2 tpdip3 tpdin3 tpdip4 tpdin4 i i i i i i i i twisted-pair data inputs (positive and negative). these pins are the positive (tpdip1- 4) and negative (tpdin1-4) inputs from the network to the respective twisted-pair ports. table 2. aui port signal descriptions pin symbol i/o description 28 29 auidop auidon o o aui data outputs (positive and negative) . these pins are the positive and negative data outputs from the aui port. 30 31 auidip auidin i i aui data inputs (positive and negative). these pins are the positive and negative data inputs to the aui port. 32 33 auicip auicin i i aui collision inputs (positive and negative). these pins are the positive and negative collision inputs to the aui port. table 3. control, status and miscellaneous signal descriptions pin symbol i/o description 2sysclki system clock . the required 20 mhz system clock is input at this pin. clock must have a 40-60 duty cycle with <10 ns rise time. 10 reset i reset . this pin resets the lxt915 internal circuitry when pulled or driven high for 1 ms. 11 dsqe i disable sqe. when high the sqe function is disabled. 7 24 ledm0 ledm1 i i led mode select 0 & 1. these two pins select one of four possible modes of led operation. the functional description section describes the four modes and table 6 lists the four settings. 17 ledcf o collision & fifo error led driver. this tri-state led driver pin reports collisions and fifo errors. it pulses low to report collisions, and pulses high to report fifo errors. when this pin is connected to the anode of one led and to the cathode of a second led, the lxt915 will simultaneously monitor and report both conditions independently.
lxt915 ? simple quad ethernet repeater 10 datasheet 18 19 20 21 ledtp1 ledtp2 ledtp3 ledtp4 o o o o tp port led drivers. these tri-state led drivers use an alternating pulsed output to report tp port status. each pin should be tied to a pair of leds (to the anode of one led and the cathode of a second led). when connected this way, each pin reports five separate conditions (receive, transmit, link integrity, reverse polarity and auto partition). 22 ledaui o aui port led driver. this tri-state led driver uses an alternating pulsed output to report aui port status. this pin should be tied to a pair of leds (to the anode of one led and the cathode of a second led). when connected this way, this pin reports five separate conditions (receive, transmit, receive jabber, receive collision and auto partition). 4 5 8 12 13 14 nc _ no connects . leave these pins unconnected (mandatory). table 4. inter-repeater backplane signal descriptions pin symbol i/o description 1bclkioi/o backplane clock. this 10 mhz clock synchronizes multiple repeaters on a common backplane. in the synchronous mode, bclkio must be supplied to all repeaters from a common external source. in the asynchronous mode, bclkio is supplied only when a repeater is outputting data to the bus. each repeater outputs its internally recovered clock when it takes control of the bus. other repeaters on the backplane then sync to bclkio for the duration of the transmission. 3a/sync i backplane synch mode select. this pin selects the backplane synch mode. when this pin is left floating an internal pull-up defaults to the asynchronous mode (a/sync high). in the asynchronous mode 12 or more lxt915s can be connected on the backplane, and an external 10 mhz backplane clock source is not required. when the synchronous mode is selected (a/sync tied low), 32 or more lxt915s can be connected to the backplane and an external 10 mhz backplane clock source is required. 59 irena i/o inter-repeater backplane enable. this pin allows individual lxt915 repeaters to take control of the inter-repeater backplane (irb) data bus (irdat). the irena bus must be pulled up locally by a 330 ? resistor. 1 60 irdat i/o irb data. this pin is used to pass data between multiple repeaters on the irb. the irdat bus must be pulled up locally by a 330 ? resistor. 1 61 irden o irb driver enable. the irden pin is used to enable external bus drivers which may be required in synchronous systems with large backplanes. this is an active low signal, maintained for the duration of the data transmission. irden must be pulled up locally by a 330 ? resistor. 62 63 ircfs ircol i/o i/o irb collision flag sense (ircfs ) and irb collision (ircol ) . these two pins are used for collision signalling between multiple lxt915 devices on the irb. both the ircfs bus and the ircol bus must be pulled up globally with 330 ? resistors. 1 (ircfs requires a precision resistor [1%].) 2 1. irena and irdat can be buffered between boards in multi-board configurations. where buffering is used, a 330 ? pull-up resistor can be used on each signal, on each board. where no buffering is used, the total impedance should be no less than 330 ? . 2. ircfs and ircol cannot be buffered. in multi-board configurations, the total impedance on ircol should be no smaller than 330 w. ircfs should be pulled up only once, by a single 330 ? , 1% resistor. table 3. control, status and miscellaneous signal descriptions (continued) pin symbol i/o description
simple quad ethernet repeater ? lxt915 datasheet 11 table 5. lxt915 power supply signal descriptions pin symbol i/o description 15 16 37 43 55 56 57 58 vcc _ power supply. these pins each require a +5 vdc power supply. these various pins may be supplied from a single power source, but special de-coupling requirements may apply. each vcc pin must be within 0.3 v of every other vcc pin. 6 9 23 25 27 34 40 46 64 gnd _ ground. these pins provide ground return paths for the various vcc power supply pins. connect these pins to external ground (mandatory). 26 rbias i bias . this pin provides bias current for internal circuitry. connect this pin to ground through an external 12.4k 1% resistor.
lxt915 ? simple quad ethernet repeater 12 datasheet 2.0 lxt915 functional description 2.1 introduction the lxt915 is an integrated hub repeater for 10base-t networks. the hub repeater is the central point for information transfer across the network. the lxt915 offers multiple operating modes to suit a broad range of applications from simple 4-, 8- or 16-port stand-alone models up to 128-port stackable hubs. the main functions of the lxt915 hub repeater are data recovery and retransmission and collision propagation. data packets received at the aui or 10base-t ports are detected and recovered by the port receivers before being passed to the repeater core circuitry for retiming and retransmission. data packets received through the irb port are essentially passed directly to the core for retransmission. after recovery of a valid data packet, the repeater broadcasts it to all enabled stations, except the originator station. 2.2 external interfaces the lxt915 includes four 10base-t ports with internal filters. the lxt915 also includes an attachment unit interface (aui) port and an inter-repeater backplane (irb) port. the irb port enables multiple lxt915 devices to be interconnected, creating a large, single-segment, multi-port repeater. 2.2.1 10base-t ports the four 10base-t transceiver ports are completely self-contained. since the transmitters and receivers include the required filtering, only simple, inexpensive transformers are required to complete the 10base-t interface. each individual twisted-pair (tp) port is implemented in accordance with the ieee 802.3 10base-t standard. refer to table 1 for tp port signal descriptions. 2.2.2 aui port the aui port operates in standard dte mode and allows connection of an external transceiver (10base-2, 10base-5, 10base-t or foirl) or a drop cable. refer to table 2 for aui port signal descriptions. 2.2.3 inter-repeater backplane the inter-repeater backplane (irb) allows several lxt915s to function as a single repeater. the irb also allows several multi-repeater boards to be integrated in a standard rack and to function as a single unit. the irb supports ? hot swapping ? for easy maintenance and troubleshooting. each individual repeater distributes recovered and retimed data to other repeaters on the irb for broadcast on all ports simultaneously. this simultaneous rebroadcast allows the multi-repeater system to act as a single large repeater unit. the maximum number of repeaters on the irb is
simple quad ethernet repeater ? lxt915 datasheet 13 limited by bus loading factors such as parasitic capacitance. the irb can be operated synchronously or asynchronously. refer to table 3 for control signals and to table 4 for irb signal descriptions. 2.2.3.1 synchronous irb operation in the synchronous mode, a common external source provides the 10 mhz backplane clock (bclkio) and the 20 mhz system clock (sysclk) to all repeaters. (bclkio must be synchronous to sysclk and may be derived from sysclk using a divide-by-two circuit.) in the synchronous mode 32 or more lxt915 repeaters may be connected on the irb, providing 128 10base-t ports and 32 aui ports. 2.2.3.2 asynchronous irb operation in the asynchronous mode an external bclkio source is not required. the repeaters run independently until one takes control of the irb. the transmitting repeater then outputs its own 10 mhz clock onto the bclkio line. all other repeaters sync to that clock for the duration of the transmission. in the asynchronous mode 12 or more lxt915 devices may be connected to the irb, providing 48 10base-t ports and 12 aui ports. note: the maximum number of repeaters which may be linked on the backplane is limited by board design factors. the numbers listed above are engineering estimates only. stronger drivers and reduced capacitive loading in pcb layout may allow an increased device count. 2.3 internal repeater circuitry the basic repeater circuitry is shared among all the ports within the lxt915. it consists of a global repeater state machine, several timers and counters and the timing recovery circuit. the timing recovery circuit includes a fifo for retiming and recovery of the clock which is used to clock the receive data out onto the irb. the shared functional blocks of the lxt915 are controlled by the global state machine shown in figure 3 . this diagram and all associated notations used are in strict accordance with section 9.6 of the ieee 802.3 standard. the lxt915 also implements the partition state diagram as defined by the ieee 802.3 standard and shown in figure 4 . the value of cc limit as implemented in the lxt915 is 64. the cc limit value sets the number of consecutive collisions that must occur before the port is subjected to automatic partitioning. auto-partition/reconnection is also supported by the lxt915 with tw5 conforming to the standard requirement of 450 to 560 bit times.
lxt915 ? simple quad ethernet repeater 14 datasheet 2.4 initialization the following description applies to the initial power-on reset and to any subsequent hardware reset. when a reset occurs (reset pin pulled high for > 1 ms), the device senses the levels at the various control pins ( table 3 and table 4 ) to determine the correct operating modes for the leds and the irb. figure 3. global state machine out (allxn) = preamble pattern send preamble pattern out (all) = idle idle begin start out (allxn) = twoones send two ones out (allxn) = data send data out (all) = jam transmit collision out (allxm) = jam one port left starttw1 out(all) = idle wait out (allxn) = jam receive collision power on uct collin(any) = sqe[n port(collin = sqe)] collin(anyxn) = sqe collin(anyxn) = sqe collin(n) = sqe + datain(n) = ii * collin (all) = sqe collin(anyxn) = sqe collin(anyxn) = sqe collin(anyxm) = sqe collin(any) = sqe + tw1done collin(only1) = sqe * tt(all) ? 96:[m port(collin = sqe)] datain(any) = ii * collin(all) = sqe:[n port(datain = ii)] tt(allxn) ? 62 * datardy * collin(all) = sqe * datain(n) = ii collin(n) = sqe + datain(n) = ii * collin(all) = sqe * alldatasent * tt(anayxn) < 96 collin(n) = sqe + datain = ii * collin(all) = sqe twoonessent * collin(all) = sqe * datain(n) = ii collin(all) = sqe * tt(all) ? 96 * tw2done datain(m) = ii* collin(all) = sqe* tw2done datain(n) = ii * collin(all) = sqe * tt(allxn) ? 96 * tw2done datain(n) = ii * collin(all) = sqe * tt(allxn) ? 96 * alldatasent ii = input_idle (no activity) ii = activity
simple quad ethernet repeater ? lxt915 datasheet 15 figure 4. partitioning state diagram partition wait datain(x) = ii collin(x) = sqe partition hold datain(x) = ii collin(x) = sqe dipresent(x) = ii *cipresent(x) = sqe dipresent(x) = ii + cipresent(x) = sqe cipresent(x) = sqe dipresent(x) = ii cipresent = sqe partition collision watch datain(x) = ii collin(x) = sqe starttw5 wait to restore port datain(x) = ii collin(x) = sqe cc(x) = 0 tw5done * dipresent(x) = ii * cipresent(x) = sqe count clear cc(x) = 0 datain(x) = dipresent(x) collin(x) = cipresent(x) begin collision count idle datain(x) = dipresent(x) collin(x) = cipresent(x) dipresent(x) = ii * cipresent(x) = sqe watch for collision starttw5 datain(x) = dipresent(x) collin(x) = cipresent(x) collsion count increment datain(x) = dipresent(x) collin(x) = cipresent(x) cc(x) = cc(x) + 1 starttw6 dipresent(x) = ii * cipresent(x) = sqe tw5done * dipresent(x) = ii * cipresent(x) = sqe dipresent(x) = ii + cipresent(x) = sqe cipresent(x) = sqe cc(x) cclimit + (tw6done * cipresent(x) = sqe) dipresent(x) = ii * cipresent(x) = sqe * cc(x) < cclimit * tw6done dipresent(x) = ii * cipresent (x) = sqe
lxt915 ? simple quad ethernet repeater 16 datasheet 2.5 10base-t port operation 2.5.1 10base-t reception each lxt915 10base-t port receiver acquires data packets from its twisted-pair input (dip/ din). an internal rc filter and an intelligent squelch function discriminate noise from link test pulses and valid data streams. no external filters are required. the receive function is activated only by valid data streams (above the squelch level and with proper timing). if the differential signal at the di circuit inputs falls below 75% of the threshold level (unsquelched) for eight bit times (typical), the port receiver enters the idle state. 2.5.2 polarity detection and correction the lxt915 10base-t ports detect and correct for reversed polarity by monitoring link pulses and end-of-frame sequences. a reversed polarity condition is declared when the port receives sixteen or more incorrect link pulses consecutively, or four frames with reversed start-of-idle sequence. in these cases the receiver reverses the polarity of the signal and thereby corrects for this failure condition. if the port enters the link fail state and no valid data or link pulses are received within 96 to 128 ms, the polarity is reset to the default non-flipped condition. (if link integrity testing is disabled, polarity detection is based only on received data.) 2.5.3 10base-t link integrity testing the lxt915 fully supports the 10base-t link integrity test function. the link integrity test determines the status of the receive side twisted-pair cable. the receiver recognizes link integrity pulses transmitted in the absence of data traffic. with no data packets or link integrity pulses within 100 (50) ms, the port enters a link fail state and disables its transmitter. the port remains in the link fail state until it detects three or more data packets or link integrity pulses. 2.5.4 10base-t transmission each lxt915 10base-t port receives nrz data from the repeater core and passes it through a manchester encoder. the encoded data is then transmitted to the twisted-pair network (the do circuit). the advanced integrated pulse shaping and filtering network produces the pre-distorted and pre-filtered output signal to meet the 10 base-t jitter template. an internal continuous resistor- capacitor filter is used to remove any high-frequency clocking noise from the pulse shaping circuitry. integrated filters simplify the design work required for fcc compliant emi performance. during idle periods, the lxt915 10base-t ports transmit link integrity test pulses in accordance with the 802.3 10base-t standard. data packets transmitted by the lxt915 contain a minimum of 56 preamble bits before the start of frame delimiter (sfd). in the asynchronous mode, preamble regeneration takes place on the transmit side. in the synchronous mode, the preamble is regenerated on the receive side and distributed via the irb. if the total packet is less than 96 bits including the preamble, the lxt915 extends the packet length to 96 bits by appending a jam signal (1010...) at the end.
simple quad ethernet repeater ? lxt915 datasheet 17 2.6 aui port operation 2.6.1 aui reception the lxt915 aui port receiver acquires data packets from the network (dip/din). only valid data streams above the squelch level activate the receive function. if the differential signal at the di circuit inputs falls below 75% of the threshold level (unsquelched) for 8 bit times (typical), the aui receiver enters the idle state. 2.6.2 aui transmission the lxt915 aui port receives nrz data from the repeater core, and passes it through a manchester encoder. the encoded data then goes out on the network (dop/don). 2.7 collision handling a collision occurs when two or more repeater ports receive simultaneously, or when the aui cip/ cin signal is active. the lxt915 fully complies with the ieee 802.3 collision specifications, both in individual and multi-repeater applications. in multiple-repeater configurations, collision signaling on the irb allows all repeaters to share collision parameters, acting as a single large repeater. ircol is a digital open-drain pin. ircfs is an analog/digital port. the ircol and ircfs lines are pulled up globally (i.e., each signal requires one pull-up resistor for all boards). if there are eight 3-repeater boards in the system, all eight boards share a single pull-up resistor for ircol and a single pull-up resistor for ircfs . the global pull-up may be located on one of the boards, or on the backplane. the ircfs line requires a precision ( 1%) resistor. the irena , irdat and irden lines are each pulled up locally (one pull-up resistor per board) if external bus drivers are used. if no bus drivers are used then only one global pull-up per signal is used. 2.8 led display the led display interface consists of seven integrated led drivers, one for each of the five network ports and two for common functions. each pin provides a three-state pulsed output (+5 v, high z, and 0 v) which allows multiple conditions to be monitored and reported independently. table 6 shows the led mode selected with each ledm1 and ledm0 combination. figure 5 shows the led driver output conditions and table 7 through table 10 list the repeater states associated with each of the five conditions. 2.8.1 led mode 0 (default) this mode is selected when ledm1 and ledm0 are floated or pulled low. refer to table 7 .
lxt915 ? simple quad ethernet repeater 18 datasheet 2.8.2 led mode 1 this mode is selected when ledm1 is tied, floated or pulled low and ledm0 is pulled high by a pull-up resistor. refer to table 8 . 2.8.3 led mode 2 this mode is selected when ledm1 is pulled high by a pull-up resistor and ledm0 is floated or pulled low. refer to table 9 . 2.8.4 led mode 3 this mode is selected when ledm1 is pulled high by a pull-up resistor and ledm0 is also pulled high by a pull-up resistor. refer to table 10 . table 6. led mode selection ledm1 ledm0 led mode selected pin 24 pin 7 0 0 0 (default) 01 1 10 2 11 3 table 7. mode 0 led truth table (default) condition ledtp 1-4 ledaui ledcf 1 rx link pulse n/a fifo error 2 tx packet tx packet n/a 3 reversed polarity n/a collision 4 rx packet rx packet n/a 5 partitioned out partitioned out n/a table 8. mode 1 led truth table condition ledtp 1-4 ledaui ledcf 1 rx link pulse n/a mau jabber lockup protection (mjlp) 2n/a n/a n/a 3 n/a n/a collision 4 rx packet rx packet n/a 5n/a n/a n/a
simple quad ethernet repeater ? lxt915 datasheet 19 table 9. mode 2 led truth table condition ledtp 1-4 ledaui ledcf 1 rx link pulse n/a mau jabber lockup protection (mjlp) 2 partitioned out partitioned out n/a 3 n/a n/a collision 4 rx packet rx packet n/a 5n/a n/a n/a table 10. mode 3 led truth table condition ledtp 1-4 ledaui ledcf 1 rx link pulse n/a mau jabber lockup protection (mjlp) 2 rx packet rx packet n/a 3 partitioned out partitioned out collision 4n/a n/a n/a 5n/a n/a n/a
lxt915 ? simple quad ethernet repeater 20 datasheet figure 5. integrated led driver indications 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms condition 4: blinking red 256 ms 256 ms +5v high z 0v (gnd) 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms +5v high z 0v (gnd) condition 3: steady red +5v high z 0v (gnd) 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms condition 2: blinking green 256 ms 256 ms 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms +5v high z 0v (gnd) 4 ms condition 1: steady green 0v (gnd) 4 ms 4 ms 4 ms 93.75 ms +5v high z 4 ms 4 ms 5.33 hz 4 ms 4 ms condition 5: alternating red/green red green 820 ? 820 ? 470 ? lxt915 led driver +5 v red green 330 ? 330 ? 70 ? lxt915 led driver +5 v 2 ma operation 5 ma operation note: the drivers are capable of driving a 10 ma load. the signal is pulsed every 4 ms, making the average current approximately 5 ma.
simple quad ethernet repeater ? lxt915 datasheet 21 3.0 lxt915 application information 3.1 layout requirements 3.1.1 the twisted pair interface the four, twisted-pair output circuits are identical. each tpdop/tpdon signal has a 24.9 ?, 1%, series resistor and a 120 pf capacitor differentially across the positive and negative outputs. these signals go directly to a 1: 2 transformer creating the necessary 100 ? termination for the cable. the tpdip/tpdin signals have a 100 ? resistor across the positive and negative input signals to terminate the 100 ? signal received from the line. to calculate the impedance on the output line interface, use: (24.9 ? + 24.9 ? ) * 2 2 100 ? . the layout of the twisted-pair ports is critical in complex designs. run the signals directly from the device to the discrete termination components (located close to the transformers). the signals running from the transformers to the connector should run in close pairs directly to the connector. be careful not to cross the transmit and receive pairs. one way to avoid a problem is to run the receive pairs on the component side and the transmit pairs on the solder side. careful planning during the schematic and layout stages can avoid these problems. the pcb layout should have no ground or power planes from the transformers to the connectors. the data signals should be the only traces in this area. place the chassis ground for the connectors near the edge of the pcb, away from the signals, connecting the connector shield with the chassis. 3.1.2 the rbias pin the rbias signal sets the levels for the output drivers of the lxt915. any emissions or common mode noise entering the device here could be measured on the twisted pair output signals. the lxt915 requires a 12.4 k ?, 1% resistor directly connected to rbias at pin 26. this connection should be as short as possible. the ground rails from pins 25 & 27 should come directly off of the device to enclose the resistor and pin forming a shielded area between the rbias connection and the switching signals on the pcb. 3.2 unmanaged hub application figure 6 shows an eight-port unmanaged hub application. the application shows a pair of lxt915s connected using the asynchronous irb mode. figure 6 (sheet 1) has the lxt915 set up with the leds in mode 1 with one link led per port and a single collision led. in led mode 1, the twisted pair port leds display link integrity only (refer to table 8 ). led mode 1 is selected by pulling ledm0 high with a 1 k ? resistor on pin 7 and pulling ledm1 low with pin 24 attached to ground.
lxt915 ? simple quad ethernet repeater 22 datasheet figure 7 (sheet 2) shows the second lxt915 set up in the same led mode (mode 1). the ac/dc plug and regulator circuits are commonly used in remote hub applications. the vcc and gnd pins are at the bottom of each diagram. all vcc pins use a single power supply with decoupling capacitors installed between the vcc and gnd pins and their respective planes.
simple quad ethernet repeater ? lxt915 datasheet 23 figure 6. lxt915 8-port unmanaged hub application, led mode 1 selected (1 of 2) collision green leds link1 link2 link3 link4 1 2 3 4 5 6 7 8 cn1d rj45x4 r20 510 r21 510 r22 510 r23 510 d1 yellow led d2 d3 d4 d5 r24 510 vcc r13 330 r14 330 r16 330 1% irena irdat ircfs ircol vcc r15 330 r25 1k vcc nc 14 nc 12 nc 5 ledm0 7 nc 8 irena* 59 irdat 60 irden* 61 ircfs* 62 ircol* 63 sysclk 2 bclkio 1 reset 10 a/sync* 3 nc 13 rbias 26 auidon 29 auidop 28 auidin 31 auidip 30 auicin 33 auicip 32 tpdin4 47 tpdip4 48 tpdin3 49 tpdip3 50 tpdin2 51 tpdip2 52 tpdin1 53 tpdip1 54 tpdon4 35 tpdop4 36 tpdon3 39 tpdop3 38 tpdon2 41 tpdop2 42 tpdon1 45 tpdop1 44 ledcf 17 nc 4 ledtp1 18 ledtp2 19 ledtp3 20 ledtp4 21 ledaui 22 ledm1 24 dsqe 11 u1 lxt915pc led mode 1 selected out 8 y1 20mhz_osc r49 22 reset 20mhz bclkio vcc r26 12.4k 1% 1 2 s1 pb_switch r50 22 r5 24.9 1% r6 24.9 1% r7 24.9 1% r8 24.9 1% r9 24.9 1% r10 24.9 1% r11 24.9 1% r12 24.9 1% r1 100 1% r4 100 1% c2 120pf c3 120pf c4 120pf c5 120pf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 t1 rx1:1x4 tg01-1006n2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 t2 tx1:1.41x4 tg54-1006n2 tp1 tp2 tp3 1 2 3 4 5 6 7 8 cn1b rj45x4 1 2 3 4 5 6 7 8 cn1c rj45x4 tp4 1 2 3 4 5 6 7 8 cn1a rj45x4 j1 bnc cgnd r2 100 1% r3 100 1% cd+ 1 cd- 2 rx+ 3 rx- 6 tx+ 7 tx- 8 vee 4 vee 5 vee 13 rr+ 11 rr- 12 cds 16 rxi 14 txd 15 hbe 9 gnd 10 u2 dp8392 r28 1k d6 1n4148 r19 78.7 1% 1% 1 1 2 2 4 4 5 5 7 7 8 8 9 9 10 10 12 12 13 13 15 15 16 16 t5 tg01-0756 r51 1.5k r52 1.5k r53 1.5k r54 1.5k r17 78.7 1% r18 78.7 1% vin+ 1 vin+ 2 en 3 vin- 23 vin- 24 vo+ 12 vo- 9 u3 pm6044 vcc r27 1meg c6 spark gap 1-3kv c1 .001uf bnc
lxt915 ? simple quad ethernet repeater 24 datasheet figure 7. lxt915 8-port unmanaged hub application led mode 1 selected (2 of 2)
simple quad ethernet repeater ? lxt915 datasheet 25 3.3 magnetics requirements 3.3.1 the twisted pair interface the lxt915 requires transformers with a 1:1 ratio for the receive pairs and 1: 2 on the transmit pairs. the transformer isolation voltage should be rated at 2 kv to protect the circuitry from static voltages across the connectors and cables. magnetics suitable for the lxt915 are currently available, and are used on the lxt914 quad repeater. available magnetics include the following options: simple per-port rx/tx pair transformers receive quad transformers and transmit quad transformers single 40 pin octal transformers 3.3.2 component selection table 11 is a list of available quad and single port transformers with manufacturers and part numbers. this information was valid as of the printing date of this document. before committing to a specific component, designers should contact the manufacturer for current product specifications, and should test and validate the magnetics for the specific application. table 11. manufacturers magnetics list manufacturer quad transmit quad receive quad port tx/rx bel s553-5999-02 s553-5999-03 halo td54-1006l1 tg54-1006n2 td01-1006l1 tg01-1006n2 tg44-s010nx tg45-s010nx tg46-s010nx nanopulse 5976 5977 kappa tp4003p tp497p101 pca epe6009 epe6010 tdk tla-3t107 tla-3t106 valor pt4116 pt4117
lxt915 ? simple quad ethernet repeater 26 datasheet 4.0 lxt915 test specifications note: table 12 through table 19 and figure 8 represent the performance specifications of the lxt915. these specifications are guaranteed by test except where noted ? by design. ? minimum and maximum values listed in table 14 through table 19 apply over the recommended operating conditions specified in table 13 . . table 12. absolute maximum ratings parameter symbol min typ max units supply voltage v cc -0.3 ? 6v operating temperature t op 0 ? +70 c storage temperature t st -65 ? +150 c note: exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 13. recommended operating conditions parameter symbol min typ max units recommended supply voltage v cc 4.75 5.0 5.25 v recommended operating temperature t op 0 ? 70 c table 14. i/o electrical characteristics 1 parameter symbol min typ 2 max units test conditions supply current i cc ?? 240 3 ma 100 ? test load on tpos, no leds input low voltage v il ?? 0.8 v input low voltage (reset) v ilreset ?? 0.8 v v cc = 5.25 v input high voltage v ih 2.0 ?? v input high voltage (reset) v ihreset 4.0 ?? vv cc = 4.75 v output low voltage v ol ?? 0.4 v i ol = 1.6 ma output low voltage v ol ?? 10 % v cc i ol < 10 a output low voltage (led) v oll ?? 1.0 v i oll = 5 ma output high voltage v oh 2.4 ?? vi oh = 40 a output high voltage v oh 90 ?? % v cc i oh < 10 a output high voltage (led) v ohl 4 ?? vi ohl = -5 ma input low current i il ?? 2mav ol = .4 v output rise / fall time ?? 38nsc load = 20 pf reset pulse width pw reset 1.0 ?? ms v cc = 4.75 v reset fall time tf reset ?? 20.0 sv ihreset to v ilreset 1. not applicable to irb signals; irb electrical characteristics are specified in table 17 . 2. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 3. supply current may vary depending on the transformer, led, and resistor selections.
simple quad ethernet repeater ? lxt915 datasheet 27 table 15. aui electrical characteristics parameter symbol min typ 1 max units test conditions input low current i il ?? -700 a input high current i ih ?? 500 a differential output voltage v od 550 ? 1200 mv receive input impedance z in ? 20 ? k ? between cip/cin & dip/din differential squelch threshold v ds ? 220 ? mv 1. typical values are at 25 c and are for design aid only; they are not guaranteed and no subject to production testing. table 16. tp electrical characteristics parameter symbol min typ 1 max units test conditions transmit output impedance z out ? 5 ? ? peak differential output voltage v od 3.3 3.5 3.7 v load = 100 ? at tpop and tpon transmit timing jitter addition ?? 6.4 10 ns 0 line length transmit timing jitter added by the mau and pls sections 2 ?? 3.5 5.5 ns after line model specified by ieee 802.3 for 10base-t receive input impedance z in ? 20 ? k ? between tpip/tpin differential squelch threshold v ds 300 420 565 mv 5 mhz square wave input 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 2. ieee 802.3 specifies maximum jitter additions at 1.5 ns for the aui cable, 0.5 ns from the encoder, and 3.5 ns from the mau. table 17. irb electrical characteristics parameter sym min. typ 1 max units test conditions output low voltage v ol ? 0.3 0.6 v output rise or fall time t rf ? 412ns input low voltage: irena , ircol & irdat v ilirb ?? 0.8 v r l = 330 ? input high voltage: irena , ircol & irdat v ihirb 3.0 ?? vr l = 330 ? input low voltage: bclkio v ilbclk ?? 0.4 v r l = 330 ? input high voltage: bclkio v ihbclk 4.0 ?? vr l = 330 ? 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing.
lxt915 ? simple quad ethernet repeater 28 datasheet table 18. switching characteristics parameter min typ 1 max units jabber timing maximum transmit time 5.0 ? 5.5 ms unjab time ? 9.6 ? s link integrity timing time link loss ? 60 ? ms time between link integrity pulses 10 ? 20 ms interval for valid receive link integrity pulses 4.1 ? 30 ms 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing.
simple quad ethernet repeater ? lxt915 datasheet 29 figure 8. inter-repeater bus timing table 19. inter-repeater bus timing parameter symbol min typical 1 max. units start of frame to irden low (active) tirb1 10 ? 150 ns start of frame to irena low (active) tirb2 125 ? 225 ns bclkio to irdat valid (synchronous mode) tirb3 5 ? 30 ns bclkio to irdat valid (asynchronous mode) tirb3 ? 50 ? ns irena low (active) to tp outputs active tirb4 525 ? 600 ns irena low (active) to aui output active tirb5 475 ? 525 ns end of frame clock to irena high (inactive) tirb6 5 ? 30 ns irena high (inactive) to irden high (inactive) tirb7 95 ? 105 ns irena high (inactive) to tp outputs inactive tirb8 575 ? 600 ns irena high (inactive) to aui output inactive tirb9 425 ? 450 ns 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. t irb8 t irb4 t irb5 t irb9 t irb7 t irb2 t irb1 t irb6 t irb3 bclkio irdat irena irden aui tps rx data
lxt915 ? simple quad ethernet repeater 30 datasheet 5.0 lxt915 mechanical specifications figure 9. lxt915 package specifications d d 1 e e 1 e / 2 e a 2 l a b l 1 3 3 a 1 dim inches millimeters min max min max a ? 0.130 ? 3.30 a 1 0.000 0.01 0.000 0.025 a 2 0.100 0.110 2.55 3.05 b 0.012 0.018 0.30 0.45 d 0.695 0.715 17.65 18.15 d 1 0.547 0.551 13.90 14.00 e 0.695 0.715 17.65 18.15 e 1 0.547 0.555 13.90 14.10 e 0.032 bsc 0.80 bsc l 0.026 0.037 0.65 0.95 l 1 0.077 ref 1.95 ref 0 7 0 7 3 5 16 5 16 p/n LXT915QC 64-pin quad flat pack temperature range 0 c - +70 c

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